1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer interconnection structure.
2. Description of Related Art
The so-called multilayer interconnection structure formed by stacking a plurality of wiring layers on a semiconductor substrate is applied to an LSI having a high degree of integration, for example. In this multilayer interconnection structure, Cu (copper) having higher conductivity is increasingly employed as a wiring material for reducing wiring resistance, in place of generally employed Al (aluminum).
In a multilayer interconnection structure (Cu interconnection structure) employing Cu as the wiring material, a first groove is dug in a first interlayer dielectric film made of SiO2 (silicon oxide) from the upper surface thereof, and a lower wire made of Cu is embedded in this first groove. A barrier film for preventing diffusion of Cu into the dielectric film is formed between the lower wire and the first interlayer dielectric film. Ta (tantalum) or TaN (tantalum nitride), for example, can be employed as the material for the barrier film. In other words, the lower wire made of Cu is embedded in the first groove formed in the first interlayer dielectric film through the Ta-based barrier film.
An SiC film made of SiC (silicon carbide) having barrier properties against diffusion of Cu is formed on the first interlayer dielectric film and the lower wire. A second interlayer dielectric film made of SiO2 is formed on the SiC film. A second groove is dug in the second interlayer dielectric film from an upper surface thereof. A via hole reaching an upper surface of the lower wire from a bottom surface of the second groove is penetratingly formed in the second interlayer dielectric film and the SiC film. Inner surfaces of the second groove and the via hole and a portion of the lower wire facing the via hole are covered with a Ta-based barrier film, so that an upper wire made of Cu is embedded in the second groove and a via made of Cu is embedded in the via hole through the barrier film respectively. Thus, the upper wire and the lower wire are electrically connected with each other through the barrier film provided between the bottom surfaces of the via hole and the via and the upper wire.
When stress is applied to the Cu interconnection structure, however, the so-called SIV (Stress Induced Voiding) may be caused to form a void (intra-via void) on a bottom portion of the via or to form a void (under-via void) immediately under the via in the lower wire made of Cu. If SIV progresses to remarkably grow the intra-via void or the under-via void, the electrical connection between the upper wire and the lower wire is disadvantageously cut.